elastic-cgra
activeElastic coarse-grained reconfigurable architectures and systolic computing for HPC and AI workloads.
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RESEARCH/
Current
research.
My work links device technology, circuit design, accelerator architecture, and HPC application mapping.
PINNED REPOSITORIES
Research areas
Three connected threads, viewed as an evolving research system.
cnfet-ocl
activeOpen-source standard cell libraries and design exploration for advanced CNFET technologies.
efficient-arithmetic
activeArea- and energy-efficient matrix multiplication, Booth encoders, adders, and accelerator datapaths.
01
FOCUS AREA
Elastic reconfigurable computing
I study elastic CGRAs as a flexible substrate for HPC and AI, with an emphasis on dataflow mapping, buffer organization, throughput, and systolic execution.
questions.md
-How can GEMM map naturally to an elastic fabric?
-Where do routing, buffering, and reconvergence limit throughput?
-How should heterogeneous compute resources be organized?
02
FOCUS AREA
Efficient arithmetic
Matrix multiplication performance is shaped by the details of its arithmetic. I explore architecture-aware multipliers, adders, MAC units, and systolic datapaths.
questions.md
-Which number representations reduce area without hurting useful accuracy?
-How do encoder choices change PPA at matrix scale?
-What optimizations survive placement and routing?
03
FOCUS AREA
Emerging devices & open cells
Advanced transistor technologies need accessible design infrastructure. My CNFET work develops and evaluates open cell libraries for realistic digital design research.
questions.md
-How do CNFET assumptions affect complete circuits?
-Can open libraries enable reproducible sub-10-nm studies?
-What is needed to extend this work toward SRAM?
DESIGN PRINCIPLE